The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, double patterning lithography (DPL) is generally used in fin field effect transistor (FinFET) fabrication processes. A conventional DPL process uses two mask patterns, a mandrel pattern and a cut pattern that removes unwanted portions of the mandrel pattern, a derivative, or both. For example, the DPL process forms a fin using the mandrel pattern and then cuts the fin into two or more sections using the cut pattern. Each section of the fin is used for forming one or more FinFETs. Different sections of the fin must be properly isolated. A conventional fin isolation process uses another patterning process to form an isolation structure between two sections of the fin. Various issues arise from these conventional processes. For example, the fin cut process may undesirably over-etch or under-etch the fin due to etching critical dimension (CD) loading and/or etching depth loading problems. Fin over-etching would reduce process window for FinFET fabrication, such as source/drain contact landing, while fin under-etching would fail to create effective fin isolation. For another example, a fin cut patterning process and an isolation patterning process may not be properly aligned, resulting in both ineffective isolation and reduced process window for FinFET fabrication. Accordingly, what is needed is a method for effectively isolating the fins while providing sufficient CD and overlay process windows for FinFET fabrication.